1. Field of the Invention
The present invention generally relates to an electronic package with a thermal interposer, and more specifically to an electronic package where a thermal interposer provides an improved thermal resistance and retains the mechanical advantages of a conventional interposer.
2. Description of the Related Art
Thermal efficiency is critical to achieving higher performance in computer chips. Achieving such thermal efficiency becomes more challenging as semiconductor electronics are being fabricated to provide a maximum amount of capability in as small a package or “footprint” as possible. In order to prevent temperature-sensitive circuits from being negatively affected by high thermal conditions, various cooling systems have been implemented in association with electronic packages.
FIG. 1 shows elements of a conventional electronic package integrated with a cooling solution. In FIG. 1, a vapor chamber heat sink 1 is formed on a surface of a multi-layer organic substrate 2. The substrate 2 is electrically connected to a printed circuit board 3 by a ball grid array 4. A thermal interface material (TIM) 5 connects the heat sink 1 with a die (“chip”) 6. Underfill 8, applied underneath and to the side of the die 6, protects a C4 (Controlled Collapse Chip Connector) area 9 that connects the die 6 to the substrate 2.
In the conventional package of FIG. 1, through the connection of the heat sink 1 and the die 6 by the thermal interface material 5, the heat sink 1 is able to remove more than 90% of heat generated through an upper silicon surface of the die 6. Polymer-based material in the organic substrate 2 limits the flow of heat through a bottom side of the die 6 since a thermal conductivity of the polymeric material in the organic substrate 2 is significantly lower than components formed with silicon or copper.
However, the remaining (or residual) 10% of the heat is inadvertently lost through the bottom side of the die 6 and is applied to areas designed for electrical interconnection but not optimized for thermal conduction, such as the ball grid array 4, the C4 area 9, and active layers of the die 6. Due to the poor thermal conductivity of the organic substrate 2, the inadvertently lost (thermal) heat energy becomes trapped in circuits where additional heat energy is not desired. Temperature-sensitive circuits especially suffer from this defect. Further, with all the heat energy being concentrated in the die 6 for escape purposes, a quality location to place temperature-sensitive circuits on the die 6 cannot be found.
FIG. 2 shows a configuration of a conventional electronic package where a conventional interposer 10 with a plurality of through vias 11 is sandwiched between a die 6 and the organic substrate 2. The substrate 2 is connected to the thermal interposer 10 by a C4 layer 9. The interposer 10 is also connected to the die 6 by a micro C4 layer 12. Underfill 8 is used to fill gaps in electrical connections made between the interposer 10, the die 6, and the organic substrate 2. The underfill 8 is formed between a surface of the substrate 2 and a surface of the die 6. Conventional underfills are generally not good thermal conductors, but help to distribute the mechanical stresses away from C4 areas.
With respect to FIG. 2, the intent of the interposer 10 is to favorably distribute mechanical stress seen by a device layer in the die 6 that occurs due to a mismatch in the coefficient of thermal expansion (CTE) between the organic substrate 2 and the die 6. A typical die has a CTE of 3 ppm per ° C., while a typical organic substrate has a CTE of approximately 18 ppm per ° C. Thus, application of heat to the organic substrate 2 and the die 6 can cause the organic substrate 2 to expand six times more than the die 6. The differential expansion of the die 6 and the substrate 10 generates large shear stress at the respective mating surfaces of the underfill. Also, the shear stress is then transferred to a device layer (not shown), where the stress could cause the cracking of transistors fabricated within the device layer. Chip warp and deformation also occur due to differential expansion.
The planar area (or footprint) of a conventional interposer 10 matches that of the die 6. In this configuration, when the CTE of the die 6 and conventional interposer 10 are matched, the interposer 10 provides a mechanical advantage. The shear stress is minimized due to reduced differential expansion. The favorable distribution of mechanical stress can increase the reliability of both the micro-C4 layer 12 and the device layer. However, the C4 layer 9 is not protected because the differential expansion between the organic substrate 2 and the conventional interposer 10 is not reduced by this configuration.
The effects of a conventional interposer on warping of the chip are demonstrated in FIG. 3. Specifically, as shown, when a die has a diagonal distance of around 13 mm and is not influenced by a conventional interposer, the typical chip warp reaches around 90 μm. On the contrary, when a conventional interposer is fabricated of silicon and is introduced between a die and an organic substrate, the chip warp is significantly reduced. For example, with the conventional interposer made of silicon, at the same diagonal distance as specified for the die above, the chip warp reaches around 55 μm, which is a reduction of 39% from a chip not having a conventional interposer.
The effects of a conventional interposer on mechanical stress are demonstrated in FIG. 4. Specifically, as shown, when a die is not influenced by a conventional interposer, a principal device stress, which is the stress in a device layer, is around 45 MPa, and a device peak corner shear stress, which is the shear stress in a device layer, is around 73 MPa. On the contrary, when a conventional interposer having a 50 μm thickness of silicon is introduced into a relationship between a die and an organic substrate, a device principal stress drops by 31% to about 30 MPa and a device peak corner shear stress drops by 58% to about 32 MPa.
While additional thickness fails to substantially affect the device principal stress, the device peak corner shear stress is significantly affected by an increased thickness of a conventional interposer. Specifically, where a thermal interposer having a 730 μm thickness of silicon is introduced in between a die and an organic substrate, a device principal stress drops slightly to about 28 MPa. The device peak corner stress, on the other hand, drops to about 1 MPa. Therefore, while the principal stress is not significantly affected by further increases in silicon thickness, an increase in silicon thickness still can further prevent the chip warp by significantly decreasing the device peak corner stress.
While the conventional interposer including silicon has all increased principal stress level pursuant to the thickness of the interposer, such an increase in principal stress, even where a conventional interposer is made of 730 μm thick silicon and experiences 80 MPa of principal stress, is perfectly acceptable. The silicon interposer can withstand a level of stress around 200 MPa without developing a crack. In this situation, the interposer is simply acting as a buffer modulating the difference in CTE between the organic substrate and die, and has no active device layer to risk any failure.
Nevertheless, as is shown in FIG. 5, despite all the mechanical benefits and advantages of including a conventional interposer in an electronic package, the conventional interposer fails to substantially contribute to a steady state thermal enhancement of the chip.
FIG. 5 shows a configuration of a conventional electronic package as is shown in FIG. 2 where a conventional interposer 10 with a plurality of through vias 11 is sandwiched between a die 6 and an organic substrate 2. The substrate 2 is connected to the conventional interposer 10 by a C4 layer 9. The conventional interposer 10 is also connected to a device layer 13 of the die 6 by a micro C4 layer 12. The die 6 is formed on a surface of the device layer 13, and a thermal interface material 5 is formed on a surface of the die 6. Underfill 8 is used to fill gaps surrounding the electrical connections of the C4 9 and micro C4 12 layers made between the conventional interposer 10, the die 6, and the organic substrate 2.
However, FIG. 5 shows that, despite the ability of the conventional interposer 10 to reduce stress associated with CTE in an electronic package, the conventional interposer 10 fails to positively influence conventional heat flux path A to reduce the amount of heat that is inadvertently lost and escaping through the bottom portion of the die. In fact, the conventional interposer 10 slightly reduces an amount of residual heat conducted through the organic substrate 2 by increasing a thermal resistance.